5.00
(1 Rating)

Mapping Signal Processing Algorithms to Architecture

Wishlist Share
Share Course
Page Link
Share On Social Media

About Course

Mapping Signal Processing Algorithms to Architecture

Digital signal processing usually entails performing repetitive computations on streams of incoming data while keeping in mind restrictions such as sampling rate and desired throughput. Such systems are frequently required to be constructed under strict time, resource, power, or cost limitations. When utilized in embedded systems, custom designs with considerably superior cost-to-benefit ratios than general-purpose computing architectures are typically worth the effort.

This course examines such algorithms and maps them to architectures that are either custom-designed or have unique adaptations that make them more suited to specific operations. Fundamental performance bounds, mapping to a dedicated and bespoke resource shared architectures, and approaches for automating the scheduling process are all covered. Memory access shared buses, and memory-mapped accelerators will all be investigated as part of the design. The assignments will cover a wide range of topics, from implementing and testing specifications through synthesis and scheduling utilizing high-level synthesis tools, as well as analyzing and improving the generated architectures.

Mapping Signal Processing Algorithms to Architecture Course Plan

Week 1: Review: Digital systems, digital signal processing, and computer architecture

week 2,3: DSP system models; quality metrics and bounds; number representations

Weeks 4,5,6: Implementation Time and resource constraints; allocation, binding, and scheduling strategies, Dedicated hardware; transformations; resource sharing;

Weeks 7, 8, and 9: Architectures: Programmable Systems, FSMs, and Microprograms; Instructions.

 

Join now to Mapping Signal Processing Algorithms to Architecture course.

Show More

Course Content

Mapping Signal Processing Algorithms to Architecture

  • Implementation Costs and Metrics
    12:00
  • Architecture cost components
    05:25
  • Number representation
    07:01
  • Scientific notation and Floating point
    12:23
  • Retiming basic concept
    05:16
  • Pipelining
    13:52
  • Valid pipelining examples
    09:03
  • Constraint analysis for IPB computation
    18:25
  • Power consumption
    04:48
  • General IPB computation
    11:29
  • DEMO: FFT synthesis
    11:44
  • Examples with formulation
    08:09
  • DEMO: FFT in Vivado HLS
    13:46
  • Mathematical formulation
    11:59
  • Hardware assumptions and constraint analysis
    13:47
  • Changing iteration period
    05:00
  • Resource sharing: adder example
    17:53
  • DEMO: Analyze FFT implementation
    11:04
  • Iteration period bound and schedulingsson
    12:49
  • ALAP schedule
    08:03
  • Allocation, Binding and Scheduling
    15:43
  • Retiming for scheduling
    09:02
  • Improved blocked schedule
    07:11
  • Obtaining a folding schedulen
    13:50
  • Scheduling: problem formulation
    15:31
  • Force Directed Scheduling
    31:07
  • DEMO: FFT Simulation and Optimizationson
    21:41
  • ILP formulation
    11:41
  • Heuristic approaches to scheduling
    16:29
  • Mathematical formulation
    15:08
  • DEMO: HLS on FFTon
    15:45
  • Example: differential equation solver
    08:44
  • Software Compilation
    16:43
  • Optimization Examples
    22:03
  • Loop optimizations 1
    18:27
  • Loop optimizations 2
    20:10
  • Background: CPUs and FPGAs
    24:57
  • Demo: FFT on FPGA board
    28:18
  • Demo: Vivado setupn
    14:57
  • Demo: Vivado ILA and VIO on hardware
    19:18
  • AXI bus handshaking
    21:12
  • AXI bus (contd)
    18:07
  • Demo: HW accelerator for FPGA
    21:50
  • DMA and arbitration
    23:38
  • NoC – topologies and metrics
    21:37
  • NoC – routing
    16:12

Student Ratings & Reviews

5.0
Total 1 Rating
5
1 Rating
4
0 Rating
3
0 Rating
2
0 Rating
1
0 Rating
M
9 months ago
Wonderful lectures with great content that made me in love with the course
ResearcherStore

Want to receive push notifications for all major on-site activities?