Mapping Signal Processing Algorithms to Architecture

  • Course level: Intermediate


Mapping Signal Processing Algorithms to Architecture

Digital signal processing usually entails performing repetitive computations on streams of incoming data while keeping in mind restrictions such as sampling rate and desired throughput. Such systems are frequently required to be constructed under strict time, resource, power, or cost limitations. When utilized in embedded systems, custom designs with considerably superior cost-to-benefit ratios than general-purpose computing architectures are typically worth the effort.

This course examines such algorithms and maps them to architectures that are either custom-designed or have unique adaptations that make them more suited to specific operations. Fundamental performance bounds, mapping to a dedicated and bespoke resource shared architectures, and approaches for automating the scheduling process are all covered. Memory access shared buses, and memory-mapped accelerators will all be investigated as part of the design. The assignments will cover a wide range of topics, from implementing and testing specifications through synthesis and scheduling utilizing high-level synthesis tools, as well as analyzing and improving the generated architectures.

Mapping Signal Processing Algorithms to Architecture Course Plan

Week 1: Review: Digital systems, digital signal processing, and computer architecture

week 2,3: DSP system models; quality metrics and bounds; number representations

Weeks 4,5,6: Implementation Time and resource constraints; allocation, binding, and scheduling strategies, Dedicated hardware; transformations; resource sharing;

Weeks 7, 8, and 9: Architectures: Programmable Systems, FSMs, and Microprograms; Instructions.


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Topics for this course

46 Lessons

Mapping Signal Processing Algorithms to Architecture

Implementation Costs and Metrics12:00
Architecture cost components5:26
Number representation7:01
Scientific notation and Floating point00:12:23
Retiming basic concept00:05:16
Valid pipelining examples00:09:03
Constraint analysis for IPB computation00:18:25
Power consumption00:04:48
General IPB computation00:11:29
DEMO: FFT synthesis00:11:44
Examples with formulation00:08:09
DEMO: FFT in Vivado HLS00:13:46
Mathematical formulation00:11:59
Hardware assumptions and constraint analysis00:13:47
Changing iteration period00:05:00
Resource sharing: adder example00:17:53
DEMO: Analyze FFT implementation00:11:04
Iteration period bound and schedulingsson00:12:49
ALAP schedule00:08:03
Allocation, Binding and Scheduling00:15:43
Retiming for scheduling00:09:02
Improved blocked schedule00:07:11
Obtaining a folding schedulen00:13:50
Scheduling: problem formulation00:15:31
Force Directed Scheduling00:31:07
DEMO: FFT Simulation and Optimizationson00:21:41
ILP formulation00:11:41
Heuristic approaches to scheduling00:16:29
Mathematical formulation00:15:08
DEMO: HLS on FFTon00:15:45
Example: differential equation solver00:08:44
Software Compilation00:16:43
Optimization Examples00:22:03
Loop optimizations 100:18:27
Loop optimizations 200:20:10
Background: CPUs and FPGAs00:24:57
Demo: FFT on FPGA board00:28:18
Demo: Vivado setupn00:14:57
Demo: Vivado ILA and VIO on hardware00:19:18
AXI bus handshaking00:21:12
AXI bus (contd)00:18:07
Demo: HW accelerator for FPGA00:21:50
DMA and arbitration00:23:38
NoC – topologies and metrics00:21:37
NoC – routing00:16:12

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