Mapping Signal Processing Algorithms to Architecture

Mapping Signal Processing Algorithms to Architecture

Digital signal processing usually entails performing repetitive computations on streams of incoming data while keeping in mind restrictions such as sampling rate and desired throughput. Such systems are frequently required to be constructed under strict time, resource, power, or cost limitations. When utilized in embedded systems, custom designs with considerably superior cost-to-benefit ratios than general-purpose computing architectures are typically worth the effort.

This course examines such algorithms and maps them to architectures that are either custom-designed or have unique adaptations that make them more suited to specific operations. Fundamental performance bounds, mapping to a dedicated and bespoke resource shared architectures, and approaches for automating the scheduling process are all covered. Memory access shared buses, and memory-mapped accelerators will all be investigated as part of the design. The assignments will cover a wide range of topics, from implementing and testing specifications through synthesis and scheduling utilizing high-level synthesis tools, as well as analyzing and improving the generated architectures.

Mapping Signal Processing Algorithms to Architecture Course Plan

Week 1: Review: Digital systems, digital signal processing, and computer architecture

week 2,3: DSP system models; quality metrics and bounds; number representations

Weeks 4,5,6: Implementation Time and resource constraints; allocation, binding, and scheduling strategies, Dedicated hardware; transformations; resource sharing;

Weeks 7, 8, and 9: Architectures: Programmable Systems, FSMs, and Microprograms; Instructions.

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