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Multi-Core Computer Architecture – Storage and Interconnects

  • Course level: Beginner

Description

Multi-Core Computer Architecture – Storage and Interconnects. We are in the era of multi-core systems where even the simplest of handheld devices like a smartphone houses many processors in a single chip.

Multi-Core Computer Architecture. The core counts are ever-increasing from 8 to 10 in smartphones to over 100s in supercomputers. This course will introduce the students to the world of multi-core computer architectures. With the unprecedented growth of data science, on-chip storage systems and inter-core communication frameworks are getting equal attention as that of processors. This course will focus on delivering an in-depth exposure in memory-subsystems and interconnects of Tiled Chip Multi-Core Processors with few introductory sessions on advanced superscalar processors. The course concludes with pointers to current research standings and on-going research directions for motivating the students to explore further

 

COURSE LAYOUT

Week 1:  Fundamentals of instruction pipeline for superscalar processor design
Week 2:   Memory hierarchy design, cache memory – fundamentals and basic optimizations
Week 3: Cache memory – advanced optimizations, performance improvement techniques
Week 4:  gem5 simulator – build and run, address translations using TLB and page table
Week 5:  DRAM – organization, access techniques, scheduling algorithms, and signal systems.
Week 6:  Introduction – Tiled Chip Multicore Processors (TCMP), Network on Chips (NoC)
Week 7:  NoC router – architecture, design, routing algorithms, and flow control techniques.
Week 8:  Advanced topics in NoC and storage – compression, prefetching, QoS.

What Will I Learn?

  • Learn Multi-Core Computer Architecture – Storage and Interconnects

Topics for this course

31 Lessons

Multi-Core Computer Architecture – Storage and Interconnects

Multi-Core Computer Architecture – Storage and Interconnects [Introduction Video]00:00:00
Introduction and Overview of the Course00:00:00
Instruction Execution Principles00:00:00
Introduction to Instruction Pipeline00:00:00
Introduction to Superscalar Pipelines00:00:00
Instruction Pipeline & Performance – I00:00:00
Instruction Pipeline & Performance – II00:00:00
Introduction to Cache Memory00:00:00
Block Replacement Techniques & Write Strategy00:00:00
gem5 Simulator – An Overview00:00:00
Cache Memory00:00:00
Basic Cache Optimization Techniques00:00:00
gem5 Simulator – Cache Optimisation00:00:00
Advanced Cache Optimization Techniques-I00:00:00
Advanced Cache Optimization Techniques-II00:00:00
Cache Memory Optimizations00:00:00
Introduction to DRAM System00:00:00
DRAM Controllers & Address Mapping00:00:00
Address Translation Mechanisms00:00:00
Main Memory Concepts00:00:00
Introduction to Tiled Chip Multicore Processors00:00:00
Routing Techniques in Network On Chip00:00:00
Network On Chip Router Micro-Architecture00:00:00
gem5 Simulator – NoC Optimisation00:00:00
Energy Efficient Bufferless NoC Routers00:00:00
Sidebuffered Deflection Routers00:00:00
Concepts in Network on Chip00:00:00
QoS of NoC and Caches in TCMP Systems00:00:00
Emerging Trends in Network On Chips00:00:00
Concepts in TCMP Systems00:00:00
Multiprocessor Computer Architecture: Why, How and What’s next ?00:00:00
Multi-Core Computer Architecture
Free

Enrolment validity: Lifetime

Requirements

  • none