About Course
The Hardware Modeling using Verilog course will introduce the participants to the Verilog hardware description language. It will help them to learn various digital circuit modeling issues using Verilog, writing test benches, and some case studies.
COURSE LAYOUT
Week 1: Introduction to digital circuit design flow (3 hours)
Week 2: Verilog variables, operators, and language constructs (2 hours)
Week 3: Modeling combinational circuits using Verilog (2 hours)
Week 4: Modeling sequential circuits using Verilog (3 hours)
Week 5: Verilog test benches and design simulation (2 hours)
Week 6: Behavioral versus structural design modeling (2 hours)
Week 7: Miscellaneous modeling issues: pipelining, memory, etc. (2 hours)
Week 8: Processor design using Verilog (4 hours)
Course Content
Hardware Modeling using Verilog
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Introduction
00:00 -
Design Representation
00:00 -
Getting Started with Verilog
00:00 -
VLSI Design Styles (Part 1)
00:00 -
VLSI Design Styles (Part 2)
00:00 -
VERILOG LANGUAGE FEATURES (PART 1)
00:00 -
VERILOG LANGUAGE FEATURES (PART 2)
00:00 -
VERILOG LANGUAGE FEATURES (PART 3)
00:00 -
VERILOG OPERATORS
00:00 -
VERILOG MODELING EXAMPLES
00:00 -
VERILOG MODELING EXAMPLES (Contd)
00:00 -
VERILOG DESCRIPTION STYLES
00:00 -
PROCEDURAL ASSIGNMENT
00:00 -
PROCEDURAL ASSIGNMENT (Contd.)
00:00 -
PROCEDURAL ASSIGNMENT (EXAMPLES)
00:00 -
BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 1)
00:00 -
BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 2)
00:00 -
BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 3)
00:00 -
BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 4)
00:00 -
USER DEFINED PRIMITIVES
00:00 -
VERILOG TEST BENCH
00:00 -
WRITING VERILOG TEST BENCHES
00:00 -
MODELING FINITE STATE MACHINES
00:00 -
MODELING FINITE STATE MACHINES (Contd.)
00:00 -
DATAPATH AND CONTROLLER DESIGN (PART 1)
00:00 -
DATAPATH AND CONTROLLER DESIGN (PART 2)
00:00 -
DATAPATH AND CONTROLLER DESIGN (PART 3)
00:00 -
SYNTHESIZABLE VERILOG
00:00 -
SOME RECOMMENDED PRACTICES
00:00 -
MODELING MEMORY
00:00 -
MODELING REGISTER BANKS
00:00 -
BASIC PIPELINING CONCEPTS
00:00 -
PIPELINE MODELING (PART 1)
00:00 -
PIPELINE MODELING (PART 2)
00:00 -
SWITCH LEVEL MODELING (PART 1)
00:00 -
SWITCH LEVEL MODDELING (PART 2)
00:00 -
PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 1)
00:00 -
PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 2)
00:00 -
PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 3)
00:00 -
VERILOG MODELING OF THE PROCESSOR (PART 1)
00:00 -
VERILOG MODELING OF THE PROCESSOR (PART 2)
00:00
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