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Hardware Modeling using Verilog

  • Course level: Beginner

Description

The Hardware Modeling using Verilog course will introduce the participants to the Verilog hardware description language. It will help them to learn various digital circuit modeling issues using Verilog, writing test benches, and some case studies.

COURSE LAYOUT

Week 1: Introduction to digital circuit design flow (3 hours)

Week 2: Verilog variables, operators, and language constructs (2 hours)

Week 3: Modeling combinational circuits using Verilog (2 hours)

Week 4: Modeling sequential circuits using Verilog (3 hours)

Week 5: Verilog test benches and design simulation (2 hours)

Week 6: Behavioral versus structural design modeling (2 hours)

Week 7: Miscellaneous modeling issues: pipelining, memory, etc. (2 hours)

Week 8: Processor design using Verilog (4 hours)

 

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Topics for this course

41 Lessons

Hardware Modeling using Verilog

Introduction00:00:00
Design Representation00:00:00
Getting Started with Verilog00:00:00
VLSI Design Styles (Part 1)00:00:00
VLSI Design Styles (Part 2)00:00:00
VERILOG LANGUAGE FEATURES (PART 1)00:00:00
VERILOG LANGUAGE FEATURES (PART 2)00:00:00
VERILOG LANGUAGE FEATURES (PART 3)00:00:00
VERILOG OPERATORS00:00:00
VERILOG MODELING EXAMPLES00:00:00
VERILOG MODELING EXAMPLES (Contd)00:00:00
VERILOG DESCRIPTION STYLES00:00:00
PROCEDURAL ASSIGNMENT00:00:00
PROCEDURAL ASSIGNMENT (Contd.)00:00:00
PROCEDURAL ASSIGNMENT (EXAMPLES)00:00:00
BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 1)00:00:00
BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 2)00:00:00
BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 3)00:00:00
BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 4)00:00:00
USER DEFINED PRIMITIVES00:00:00
VERILOG TEST BENCH00:00:00
WRITING VERILOG TEST BENCHES00:00:00
MODELING FINITE STATE MACHINES00:00:00
MODELING FINITE STATE MACHINES (Contd.)00:00:00
DATAPATH AND CONTROLLER DESIGN (PART 1)00:00:00
DATAPATH AND CONTROLLER DESIGN (PART 2)00:00:00
DATAPATH AND CONTROLLER DESIGN (PART 3)00:00:00
SYNTHESIZABLE VERILOG00:00:00
SOME RECOMMENDED PRACTICES00:00:00
MODELING MEMORY00:00:00
MODELING REGISTER BANKS00:00:00
BASIC PIPELINING CONCEPTS00:00:00
PIPELINE MODELING (PART 1)00:00:00
PIPELINE MODELING (PART 2)00:00:00
SWITCH LEVEL MODELING (PART 1)00:00:00
SWITCH LEVEL MODDELING (PART 2)00:00:00
PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 1)00:00:00
PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 2)00:00:00
PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 3)00:00:00
VERILOG MODELING OF THE PROCESSOR (PART 1)00:00:00
VERILOG MODELING OF THE PROCESSOR (PART 2)00:00:00
Hardware Modeling using Verilog
35 £

Enrolment validity: Lifetime

Requirements

  • Non