
About Course
This course on Embedded systems will first the students to the fundamental requirements of embedded systems and the interaction between hardware and software in such systems. Next, the course will discuss some basic steps of hardware design, introduce the students to ASIPs, ASICs, and FPGAs.
Next, the students will be exposed to the very important issue of designing for less power consumption and introduce them to the techniques that are adapted to this end. Since many of the embedded systems will have real-time constraints, basic issues of real-time operating systems will be discussed. This will be followed by formal specification models and languages, mapping the specification to hardware and software components along with decisions on design tradeoffs and hardware-software partitioning. Next, the synthesis of hardware and software along with a few of the optimization techniques will be presented. The course will end with a brief overview of design verification methods that are adopted for embedded system design.
Course Content
Embedded Systems Design
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Introduction
00:00 -
Processors
00:00 -
General Purpose and ASIPs Processor
00:00 -
Designing a Single Purpose Processor
00:00 -
Optimization Issues
00:00 -
Introduction to FPFA
00:00 -
FPGA Contd.
00:00 -
Behaviour Synthesis on FPGA using VHDL
00:00 -
Tutorial – I
00:00 -
Tutorial – II
00:00 -
Tutorial – III
00:00 -
Tutorial – IV
00:00 -
Sensors and Signals
00:00 -
Discretization of Signals and A/D Converter
00:00 -
Quantization Noise, SNR and D/A Converter
00:00 -
Arduino Uno
00:00 -
Arduino Uno (Contd.), Serial Communication and Timer
00:00 -
Controller Design using Arduino
00:00 -
Tutorial – V
00:00 -
Power Aware Embedded System – I
00:00 -
Power Aware Embedded System – II
00:00 -
SD and DD Algorithm
00:00 -
Parallel Operations and VLIW
00:00 -
Code Efficiency
00:00 -
DSP Application and Address Generation Unit
00:00 -
Real Time O.S – I
00:00 -
Real Time O.S – II
00:00 -
RMS Algorithm
00:00 -
EDF Algorithm and Resource Constraint Issue
00:00 -
Priority Inversion and Priority Inheritance Protocol
00:00 -
Modeling and Specification – I
00:00 -
Modeling and Specification – II
00:00 -
FSM and Statechart
00:00 -
Statechart and Statemate Semantics
00:00 -
Statecharts (Contd.)
00:00 -
PROGRAM STATE MACHINES
00:00 -
SDL
00:00 -
Data Flow Model – I
00:00 -
Data Flow Model – II
00:00 -
Hardware Synthesis – I
00:00 -
Hardware Synthesis – II
00:00 -
Scheduling
00:00 -
Digital Camera – Iterative Design
00:00 -
HW-SW Partitioning
00:00 -
Optimization – I
00:00 -
Optimization – II
00:00 -
Simulation
00:00 -
Formal Verification
00:00
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