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Embedded Systems – Design Verification and Test

  • Course level: Intermediate

Description

Embedded Systems – Design Verification and Test.

An Embedded system (ES) can be described as a computing system that is part of a larger physical system. Examples of ESs range from a simple elevator controller to a complex avionics control system.

Unlike a general-purpose computer system, ESs are typically designed for specific functionalities, often with stringent performance objectives and constraints related to real-time accuracy, area, power, cost, etc. Their implementations may include both software and hardware components and may necessitate integration with sensors and actuators.

The increase in complexity of modern ESs mandates automation in their design. Given a system that we intend to implement, the design process majorly evolves through distinct but often overlapping and iterative phases which include, i. modeling of the intended system behavior, ii. design of appropriate structural representations and implementation methodologies, corresponding to the specified behavior, iii.

verification and validation of the correctness and performance-related properties that the designed system should satisfy, and iv. testing whether the prototyped/manufactured implementation actually performs the required behavior. The proposed course will systematically cover all these topics so that the student gains an end-to-end understanding of the overall Embedded Systems

design process.

What Will I Learn?

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Topics for this course

37 Lessons

Embedded Systems – Design Verification and Test

Embedded Systems – Design Verification and Test [Introduction Video]00:00:00
Introduction00:00:00
Modeling Techniques – 100:00:00
Modeling Techniques – 200:00:00
Hardware/Software Partitioning – 100:00:00
Hardware/Software Partitioning – 200:00:00
Introduction to Hardware Design00:00:00
Hardware Architectural Synthesis – 100:00:00
Hardware Architectural Synthesis – 200:00:00
Hardware Architectural Synthesis – 300:00:00
Hardware Architectural Synthesis – 400:00:00
Hardware Architectural Synthesis – 500:00:00
Hardware Architectural Synthesis – 600:00:00
Hardware Architectural Synthesis – 700:00:00
System Level Analysis00:00:00
Uniprocessor Scheduling – 100:00:00
Uniprocessor Scheduling – 200:00:00
Multiprocessor Scheduling – 100:00:00
Multiprocessor Scheduling – 200:00:00
Introduction and Basic Operators of Temporal Logic00:00:00
Syntax and Semantics of CTL00:00:00
Equivalence between CTL formulas00:00:00
Model Checking Algorithm00:00:00
Binary Decision Diagram00:00:00
Use of OBDDs for State Transition System00:00:00
Symbolic Model Checking00:00:00
Introduction to Digital VLSI Testing00:00:00
Automatic Test Pattern Generation (ATPG)00:00:00
Scan Chain based Sequential Circuit Testing00:00:00
Testing for embedded cores00:00:00
Bus and Memory Testing00:00:00
Testing for advanced faults in Real time Embedded Systems00:00:00
BIST for Embedded Systems00:00:00
Concurrent Testing for Fault tolerant Embedded Systems – 100:00:00
Concurrent Testing for Fault tolerant Embedded Systems – 200:00:00
Testing for Reprogrammable hardware00:00:00
Interaction Testing between Hardware and Software00:00:00
Embedded Systems
Free

Enrolment validity: Lifetime

Requirements

  • none