Embedded Systems – Design Verification and Test

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About Course

Embedded Systems – Design Verification and Test.

An Embedded system (ES) can be described as a computing system that is part of a larger physical system. Examples of ESs range from a simple elevator controller to a complex avionics control system.

Unlike a general-purpose computer system, ESs are typically designed for specific functionalities, often with stringent performance objectives and constraints related to real-time accuracy, area, power, cost, etc. Their implementations may include both software and hardware components and may necessitate integration with sensors and actuators.

The increase in complexity of modern ESs mandates automation in their design. Given a system that we intend to implement, the design process majorly evolves through distinct but often overlapping and iterative phases which include, i. modeling of the intended system behavior, ii. design of appropriate structural representations and implementation methodologies, corresponding to the specified behavior, iii.

verification and validation of the correctness and performance-related properties that the designed system should satisfy, and iv. testing whether the prototyped/manufactured implementation actually performs the required behavior. The proposed course will systematically cover all these topics so that the student gains an end-to-end understanding of the overall Embedded Systems

design process.

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Course Content

Embedded Systems – Design Verification and Test

  • Embedded Systems – Design Verification and Test [Introduction Video]
    00:00
  • Introduction
    00:00
  • Modeling Techniques – 1
    00:00
  • Modeling Techniques – 2
    00:00
  • Hardware/Software Partitioning – 1
    00:00
  • Hardware/Software Partitioning – 2
    00:00
  • Introduction to Hardware Design
    00:00
  • Hardware Architectural Synthesis – 1
    00:00
  • Hardware Architectural Synthesis – 2
    00:00
  • Hardware Architectural Synthesis – 3
    00:00
  • Hardware Architectural Synthesis – 4
    00:00
  • Hardware Architectural Synthesis – 5
    00:00
  • Hardware Architectural Synthesis – 6
    00:00
  • Hardware Architectural Synthesis – 7
    00:00
  • System Level Analysis
    00:00
  • Uniprocessor Scheduling – 1
    00:00
  • Uniprocessor Scheduling – 2
    00:00
  • Multiprocessor Scheduling – 1
    00:00
  • Multiprocessor Scheduling – 2
    00:00
  • Introduction and Basic Operators of Temporal Logic
    00:00
  • Syntax and Semantics of CTL
    00:00
  • Equivalence between CTL formulas
    00:00
  • Model Checking Algorithm
    00:00
  • Binary Decision Diagram
    00:00
  • Use of OBDDs for State Transition System
    00:00
  • Symbolic Model Checking
    00:00
  • Introduction to Digital VLSI Testing
    00:00
  • Automatic Test Pattern Generation (ATPG)
    00:00
  • Scan Chain based Sequential Circuit Testing
    00:00
  • Testing for embedded cores
    00:00
  • Bus and Memory Testing
    00:00
  • Testing for advanced faults in Real time Embedded Systems
    00:00
  • BIST for Embedded Systems
    00:00
  • Concurrent Testing for Fault tolerant Embedded Systems – 1
    00:00
  • Concurrent Testing for Fault tolerant Embedded Systems – 2
    00:00
  • Testing for Reprogrammable hardware
    00:00
  • Interaction Testing between Hardware and Software
    00:00

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