
About Course
Computer Organization & Architecture (COA) is a core course in the curricula of Computer Sciences as well as Electronics and Electrical Engineering disciplines at the second-year level in most of the Indian universities and technical institutions. This is the first course in Computer Organization & Architecture and the course would provide students with an understanding of the design of fundamental blocks used for building a computer system and interfacing techniques of these blocks to achieve different configurations of an “entire computer system”.
This Computer Organization & Architecture course will be developed and taught with respect to Objectives based on Bloom’s Taxonomy. First, we will highlight the main objectives the course is aimed to achieve. Following that, at each module, we will specify the module level objectives and demonstrate how these objectives meet the course level main goals in unison. At the leaf level i.e., the units, we will point to the specific objectives of the lecture.
Also, it will be demonstrated how the unit level objectives satisfy the parent module level objectives. Further, each module will have a module-level problem that needs concepts of all the units therein to solve. Finally, a comprehensive course-level problem related to the design of the “entire computer system” will be discussed which meets all the course-level objectives.
Course Content
Computer Organization & Architecture
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Floating Point Representation: IEEE – 754 Representation
00:00 -
Practice Questions on Cache Memory – 1
00:00 -
Computer science MultiLevel Cache
00:00 -
Cache Mapping: Types of Cache Misses
00:00 -
Cache Mapping: Cache Block Replacement
00:00 -
Cache Mapping: Hardware Implementation of Mapping
00:00 -
Cache Mapping: Set Associative Mapping & Fully Associative Mapping
00:00 -
Cache Mapping: Cache Initialization
00:00 -
Cache Mapping: Direct Mapping – 2
00:00 -
Cache Mapping: Direct Mapping – 1
00:00 -
Memory Organization: Cache Memory 2
00:00 -
Memory Organization: Cache Memory
00:00 -
Complex Problems on Instructions (COA)
00:00 -
Practice Questions on Cache Memory – 2
00:00 -
Floating Point Representation: Conventional
00:00 -
Non-Linear Pipeline
00:00 -
DPP: Instruction Pipeline
00:00 -
Pipeline Hazards & Data Hazard Classifications: RAW, WAW, WAR
00:00 -
Instruction Pipeline, Pipeline Hazards
00:00 -
DPP on Synchronous Pipeline & Pipeline
00:00 -
Parallel Processing, Flynn’s Classification & Pipelining
00:00 -
DPP on Magnetic Disk
00:00 -
Revision: Addressing Modes (COA)
00:00 -
Magnetic Disk: Disk Access Time, Disk Addressing
00:00 -
Magnetic Disk: Disk Platter, Track, Sector, Disk Access Time
00:00 -
Memory Organization: Associative Memory, Locality of Reference
00:00 -
Memory Organization: Multiple Chip Support
00:00 -
Addressing Mode – 4
00:00 -
Addressing Mode – 3
00:00 -
Addressing Mode – 2
00:00 -
Addressing Mode – 1
00:00 -
Instructions in Computer Architecture -2
00:00 -
DMA and Magnetic Disk
00:00 -
IO Organization
00:00 -
Instructions in Computer Architecture -1
00:00 -
Micro-Operations
00:00 -
CPU Registers
00:00 -
Components of Computer
00:00 -
Introduction to CPU
00:00 -
ALU & Data Path
00:00 -
Memory Organization: Memory Chip
00:00 -
Memory Organization: Main Memory & Memory Chips
00:00 -
Memory Organization: Introduction
00:00 -
DMA Modes and Problems on IO
00:00 -
IO Organization – 4
00:00 -
IO Organization – 3
00:00 -
IO Organization – 2
00:00 -
IO Organization – 1
00:00 -
Nano-programmed Control Unit
00:00 -
Types of Control Unit
00:00 -
Control Unit, Control Word, Control Unit Organization
00:00 -
Basics of Computer System
00:00