Clock Tree Synthesis

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About Course

Clock Tree Networks are Pillars and Columns of a Chip. With Clock Tree Synthesis this series of lectures, we have explored on-site concepts applied in the VLSI industry. It is a One-Stop-Shop to understand industrial VLSI circuits.

The videos will develop an analytical approach to tackle technical challenges while building the Clock Tree.

Who this course is for:

  1. Individuals keen to learn about VLSI and Chip World

What Will You Learn?

  • -CTS Quality Checks (Skew, Power, Latency, etc.)
  • -H-Tree
  • -Quality Check of H-Tree
  • -Clock Tree Buffering
  • -Buffered H-Tree
  • -H-Tree with uneven spread of Flops
  • -Advanced H-Tree for Million Flops
  • -Power Aware CTS (clock gating)
  • -Static Timing Analysis with Clock Tree

Course Content

Clock Tree Synthesis

  • What is Clock Tree Synthesis??
    00:00
  • How to do the Skew Pulse Width Quality Checks??
    00:00
  • How to do Duty Cycle Latency Quality Checks??
    00:00
  • How to do Latency Power Quality Check??
    00:00
  • How to do Power Quality Check?
    00:00
  • How to do Power Crosstalk Quality Check?
    00:00
  • What is the Delta Delay Quality Check?
    00:00
  • What is Glitch Quality Check?
    00:00
  • What is H-tree Skew Check?
    00:00
  • How to do H-Tree Pulse Width Duty Cycle Check?
    00:00
  • What is H- tree Latency Power Check?
    00:00
  • What is Clock Tree Modelling?
    00:00
  • How to do Clock Tree Buffering?
    00:00
  • How to do Clock Tree Building?
    00:00
  • How to do Clock Tree Observations?
    00:00
  • What is H- Tree Observations?
    00:00
  • How to do H-Tree Skew Check?
    00:00
  • What is H-Tree Pulse Width Check Regular And Clock Buffer?
    00:00
  • What is the Inverter Resistance Difference?
    00:00
  • What is Inverter Resistance Match Solution?
    00:00
  • H-Tree CBUF Pulse Width Check MET
    00:00
  • How to do Duty Cycle Latency Power Check?
    00:00
  • How is Dynamic Short Circuit Power Revisited?
    00:00
  • What is Leakage Power Revisit?
    00:00
  • What is the Optimization Checklist?
    00:00
  • Short Circuit Current Revisited
    00:00
  • How is Leakage Power Revisited?
    00:00
  • Clock Tree Optimized
    00:00
  • Optimized Clock Tree Power Latency Check
    00:00
  • Clock Tree Uneven Clk EndPoints Spread
    00:00
  • Logical To Physical Connection
    00:00
  • Uneven clock Endpoints HTree CheckList
    00:00
  • Advanced HTree Million Flops
    00:00
  • Power Aware CTS Intro To Gates
    00:00
  • Intro-To Delay Tables
    00:00
  • Delay Table Usage-1
    00:00
  • Delay Table Usage-2
    00:00
  • Clock Gating Using AND Gate and Skew Cal
    00:00
  • Skew Issue Solution
    00:00
  • OR_AND_simultaneous clock gating technique
    00:00
  • NAND gates as clock gating cells
    00:00
  • Clock Gating Technique on Real Chip
    00:00
  • How to do Setup timing Analysis Real Clocks?
    00:00
  • What is Data Arrival And Required Time ?
    00:00
  • Setup Timing Degrade by unbalanced Skew
    00:00
  • Hold Timing Analysis Real Clocks
    00:00
  • How is Hold Timing Degrade by unbalanced Skew?
    00:00
  • What are the steps to do CTS ?
    00:00
  • VLSI Academy CTS- CMOS Inverter PMOS/NMOS Matching Switching Resistance Solution
    00:00

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