About Course
Clock Tree Networks are Pillars and Columns of a Chip. With Clock Tree Synthesis this series of lectures, we have explored on-site concepts applied in the VLSI industry. It is a One-Stop-Shop to understand industrial VLSI circuits.
The videos will develop an analytical approach to tackle technical challenges while building the Clock Tree.
Who this course is for:
- Individuals keen to learn about VLSI and Chip World
Course Content
Clock Tree Synthesis
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What is Clock Tree Synthesis??
00:00 -
How to do the Skew Pulse Width Quality Checks??
00:00 -
How to do Duty Cycle Latency Quality Checks??
00:00 -
How to do Latency Power Quality Check??
00:00 -
How to do Power Quality Check?
00:00 -
How to do Power Crosstalk Quality Check?
00:00 -
What is the Delta Delay Quality Check?
00:00 -
What is Glitch Quality Check?
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What is H-tree Skew Check?
00:00 -
How to do H-Tree Pulse Width Duty Cycle Check?
00:00 -
What is H- tree Latency Power Check?
00:00 -
What is Clock Tree Modelling?
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How to do Clock Tree Buffering?
00:00 -
How to do Clock Tree Building?
00:00 -
How to do Clock Tree Observations?
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What is H- Tree Observations?
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How to do H-Tree Skew Check?
00:00 -
What is H-Tree Pulse Width Check Regular And Clock Buffer?
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What is the Inverter Resistance Difference?
00:00 -
What is Inverter Resistance Match Solution?
00:00 -
H-Tree CBUF Pulse Width Check MET
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How to do Duty Cycle Latency Power Check?
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How is Dynamic Short Circuit Power Revisited?
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What is Leakage Power Revisit?
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What is the Optimization Checklist?
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Short Circuit Current Revisited
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How is Leakage Power Revisited?
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Clock Tree Optimized
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Optimized Clock Tree Power Latency Check
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Clock Tree Uneven Clk EndPoints Spread
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Logical To Physical Connection
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Uneven clock Endpoints HTree CheckList
00:00 -
Advanced HTree Million Flops
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Power Aware CTS Intro To Gates
00:00 -
Intro-To Delay Tables
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Delay Table Usage-1
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Delay Table Usage-2
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Clock Gating Using AND Gate and Skew Cal
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Skew Issue Solution
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OR_AND_simultaneous clock gating technique
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NAND gates as clock gating cells
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Clock Gating Technique on Real Chip
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How to do Setup timing Analysis Real Clocks?
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What is Data Arrival And Required Time ?
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Setup Timing Degrade by unbalanced Skew
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Hold Timing Analysis Real Clocks
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How is Hold Timing Degrade by unbalanced Skew?
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What are the steps to do CTS ?
00:00 -
VLSI Academy CTS- CMOS Inverter PMOS/NMOS Matching Switching Resistance Solution
00:00
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